| 摘要 |
PURPOSE:To reduce a delay device in scale, cost, and power consumption by selecting two independent multiplex signals in every odd-numbered frame and each even-numbered frame and inputting them to a multiprocessing type delay circuit as one multiplex signal, and demultiplexing its output signal into the two independent multiplex signals again. CONSTITUTION:The output signal Q2 of a multiprocessing type counter 4 is compared by a comparator 4 with a setting signal D and the counter 4 outputs '1' as a signal Q4 when its counted value Q3 is smaller than the set value D. When the output signal Q4 of the counter 4 is '1', or when a control signal C is '1', a signal Q9, i.e. data which is one sample before is outputted as an output signal Q8. Even if a signal Q1 varies, the signal Q4 varies to '1', so the data which is one sample before is outputted as the output signal Q8; the variation is not transmitted, but the variation appears in the output signal Q5 becomes '0'. Namely, the input signal is delayed only by the set value D. |
