| 摘要 |
PURPOSE:To reduce the size of a cell and the soft error rate of alpha-rays by connecting a resistor element between the main memory node of one of inverters and the gate of a PMOS transistor which is the load of the other inverter, and by connecting a capacitor element between the drain and the gate of the load PMOS transistor. CONSTITUTION:P-type TFTMOS transistors Q1, Q2 and NMOS transistors Q3, Q4 are connected in series between a power supply Vcc and the ground, respectively, to constitute a pair of inverters l, 2. Each drain of a pair of access transistors Q5, Q6, each gate of which is connected with a word line, is connected with each main memory node (1), (2) of the inverters 1, 2. Resistor elements 3, 4 are connected between the main memory node (1), (2) of one of the inverters 1, 2 and the gate of TFTMOS transistors Q2, Q1, of the other inverter 2, 1 and capacitor elements 3, 4 are connected between the drain and the gate of TFTMOS transistors Q2, Q1, respectively. |
