发明名称 |
Digital signal processor with conditional branch decision unit and storage of conditional branch decision results |
摘要 |
A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
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申请公布号 |
US5247627(A) |
申请公布日期 |
1993.09.21 |
申请号 |
US19910750478 |
申请日期 |
1991.08.27 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MURAKAMI, TOKUMICHI;KAMIZAWA, KOH;KATOH, YOSHIAKI;OHIRA, HIDEO;KAMEYAMA, MASATOSHI;KINJO, NAOTO |
分类号 |
G06F7/575;G06F9/32;G06F9/355;G06F9/38;G06F13/28;G06F15/78 |
主分类号 |
G06F7/575 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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