| 摘要 |
The MOSFET in DRAM cell having n-source and drain formed by masking in n+ implanting, is parepared by forming a gate oxide film and a polycrystalline silicon layer at the cell and peripheral circuit area, patterning polycrystalline silicon layer to form a gate, implanting the low concn. impurity for forming a source and drain, coating photoresist thereon, exposing the peripheral circuit area, implanting the high concn. impurity at the source and the drain of the peripheral circuit area. The method decreases silicon damage because of high concn. and energy, and has a stable reflesh property.
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