The invention concerns a process for testing terminal resistances in signalling lines between emitters and receivers in ECL networks. The absence of such terminal resistances due to manufacturing faults results in deterioration in the dynamic characteristics of the circuit. Diagnostic of this type of failure is technically difficult and costly. The invention proposes a simple testing procedure based on the use of the boundary-scan cells in the components. This is done by setting all the signalling lines (S) in the network under test to logical "zero" and increasing the terminal voltages of the terminal resistances (RL) until logical "1" appears in the boundary-scan input cells (SRE) when the external test mode of the boundary-scan test procedure is applied and the terminal resistances (RL) are present, i.e. intact, and the voltages in the terminal resistances (R) in the boundary-scan lines are independent of the terminal voltages (VEE1) in the networks under test. Costly test systems can thereby be avoided and the absence or failure of the terminal resistances can be easily detected.
申请公布号
DE4210108(C1)
申请公布日期
1993.09.16
申请号
DE19924210108
申请日期
1992.03.27
申请人
SIEMENS NIXDORF INFORMATIONSSYSTEME AG, 33106 PADERBORN, DE
