发明名称 DYNAMIC MEMORY ROW/COLUMN REDUNDANCY SCHEME
摘要 A DRAM row or column decoder having a fused stage for disabling defective rows or columns. A fuse is placed within a stage preceding the final output stage of a multi-stage row or column decoder. Because the fuse is not placed within the output stage, it is not necessary to have one fuse for each individual row or column; a single fuse can disable several decoder outputs, and thus several rows or columns can be disabled at the same time.
申请公布号 US5245576(A) 申请公布日期 1993.09.14
申请号 US19910680995 申请日期 1991.04.05
申请人 FOSS, RICHARD C.;LINES, VALERIE L.;YONEYAMA, AKIRA 发明人 FOSS, RICHARD C.;LINES, VALERIE L.;YONEYAMA, AKIRA
分类号 G11C29/00 主分类号 G11C29/00
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