发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE:To provide the variable delay circuit effectively compatible with signals at different transmission speeds. CONSTITUTION:This circuit is provided with a 1st variable delay circuit 1a comprising plural unit variable delay circuits 1a-1 to 1a-4m of the same configuration and receiving an input signal and outputting the delayed signal and with a transmission speed detection circuit 2 comprising a phase comparator 22 receiving the input signal at its one input and a 2nd variable delay circuit 21 of the same configuration as that of the unit variable delay circuits and receiving the input signal. The other input of the phase comparator 22 receives the output of the 2nd variable delay circuit 21, the output of the phase comparator 22 is fed back to the delay time control terminal of the 2nd variable delay circuit 21 and fed to each of the unit variable delay circuits 1a-1 to 1a-4m+1 for a variable time control voltage of the unit variable delay circuits.
申请公布号 JPH05235714(A) 申请公布日期 1993.09.10
申请号 JP19920073434 申请日期 1992.02.25
申请人 SUMITOMO ELECTRIC IND LTD 发明人 KAMISAKA KATSUMI;TAKAHASHI SATOSHI
分类号 H03K5/13;H03K5/133 主分类号 H03K5/13
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