| 摘要 |
The capacitor structure of a DRAM cell includes a substrate for defining plural active regions and field regions, plural word lines arranged by a predetermined interval on the active region of the substrate by twos in one direction, plural bit lines arranged one by one on one active region vertical to the word line spaced by a predetermined interval, plural bit line contact regions for respectively connecting the active region and bit line between two word lines of one active region, and plural storage nodes expanding over the word line of one active region to the other word line of the other field region from the storage node contact as the reference along the bit line direction, that on the word line of the active region being wider than that on the word line of the field region, thereby increasing the area of the capacitor storage node to obtain a greater capacitance in the same area.
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