| 摘要 |
PURPOSE:To obtain a semiconductor storage device which can operate rapidly with a series resistance reduced by making the gate length of a first memory transistor(Tr) which is allowed not to conduct when it receives a low-level signal shorter than that of a second memory Tr which is allowed to conduct when it receives a low-level signal. CONSTITUTION:In a process S1, an oxide film for element isolation is formed on a silicon substrate. In a process S2, ions are injected and a threshold value of each memory Tr is determined. In a process S3, a thick gate for keeping a dielectric strength of an E-type memory Tr is formed. In a process S4, a gate electrode is etched with a mask which makes the gate length shorter and a D-type memory Tr of the desired gate length is formed. And, in a process S5, impurities are doped to form a diffusion region self-alignedly with a gate electrode of a source.drain of each Tr used as a mask. In a process S6, a contact hole is made. In a process S7, an aluminum interconnection 4 which will be a bit line is formed. In a process S8, a protective film is formed. Therefore, in a memory cell array, a series resistance is reduced only for a D-type memory Tr and thereby current increases and an operation speed is increased. |
