发明名称 DATA COMMUNICATION SYSTEM
摘要 <p>PURPOSE:To transfer data in the order smoothly by without increasing the load of the user of a line by informing a DTE of the state when the reception buffer of a DCE is fully occupied and storing the number of the DTE. CONSTITUTION:A microcomputer A controls an entire system and stores the number of a DCE whose reception is disable at the transmission and stores the information of reception disable to a memory C storing the number of an opposite party whose transmission is finished at the reception. Reception data are stored in a storage buffer F. An I/O device D interfaces a communication medium F such as a coaxial cable and the microcomputer A. The sequence timer G is used when the information of a reception disable state is received. The terminal equipment is connected to configure a network as shown in figure and acts like a DTE and a DCE. Even when plural DTEs and DCEs are connected to a data communication channel, the control at a fully occupied buffer is implemented smoothly without increasing the load of the line user.</p>
申请公布号 JPH05227212(A) 申请公布日期 1993.09.03
申请号 JP19920059337 申请日期 1992.02.12
申请人 CLARION CO LTD 发明人 TAGUCHI TAKEHIKO;MORI SEIJI
分类号 H04L12/56 主分类号 H04L12/56
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