| 摘要 |
PURPOSE: To acquire asynchronous data and to convert the data to synchronous data usable in timing type logic design by using interface state machine and data verification decoding logic. CONSTITUTION: This circuit is achieved by the three stages of micro-channel interface state machine and logic mechanisms 170, 172 and 174. In a first stage 170, control signals and data signals are acquired from an asynchronous bus, and the signals are converted to signals synchronized with the internal clocks of an interface chip. A second stage 172 is the state machine of a synchronous type and decides the present state of the asynchronous bus, by utilizing synchronization signals generated in the first stage 170. In a third stage 174, the data are verified in the synchronous type by using the data generated by the synchronous type state machine and a control signal/data signal acquisition logic mechanism. |
