发明名称 |
DYNAMIC FLOW INSTRUCTION CACHE MEMORY |
摘要 |
An improved cache (23) and organization particularly suitable for superscalar architectures. The cache (23) is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory (23) may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access. |
申请公布号 |
WO9317385(A1) |
申请公布日期 |
1993.09.02 |
申请号 |
WO1993US01634 |
申请日期 |
1993.02.23 |
申请人 |
INTEL CORPORATION |
发明人 |
PELEG, ALEXANDER;WEISER, URI |
分类号 |
G06F9/38;G06F12/08 |
主分类号 |
G06F9/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|