| 摘要 |
<p>PURPOSE:To greatly reduce a burden on software by constituting a hardware which receives data from a CPU by a FIFO memory, latches the output data of the FIFO memory in a latch circuit, and generates the output timing of the memory and latch circuit. CONSTITUTION:When the FIFO memory 2 is vacant, an RDY signal enters an enabled state. Therefore, when the CPU 1 writes data, the enabled state of the RDY signal is periodically checked and the data are written on condition that the RDY signal is in the enabled state. Once the data are written in the FIFO memory 2, the data are latched by the latch circuit 3 in the order of the writing to the FIFO memory 2 at a constant period with the timing signal of the timing generating circuit 4, and then outputted. Thus, the data in the FIFO memory 2 are outputted to the latch circuit 3 and the FIFO memory 2 becomes vacant, so that the RDY signal enters the enabled state. Consequently, the need for periodic processing by software is eliminated.</p> |
