| 摘要 |
PURPOSE: To provide an address parity generator in which the address parity of a memory bus can be generated at a high speed by the shortest transmission delay, and the applicable range of diagnosis for the error protection of an overall system can be improved with the least logic addition. CONSTITUTION: A parity generator 20 is moved to an inside bus side, the applicable range of the diagnosis is validated to both an outside bus signal and an inside bus signal. when an address register is loaded, the parity value is latched, and a DMA parity bit is updated by a state machine 26 which predicts the parity value based on the value of a present DMA counter 10 and the next address parity value. |
