发明名称 ABNORMALITY MONITOR TIMER CONTROLLER
摘要 PURPOSE:To improve the reliability by providing plural addresses to be accessed, to confirm the soundness of a program, and to easily confirm which address is not accessed owing to abnormal operation. CONSTITUTION:The abnormality monitor timer controller consists of a clear signal generating circuit 11, a power-ON reset circuit 12, an abnormality monitor timer circuit 13, a CPU 14, and an address decoder unit circuit 15, which consists of address decoder circuits 15-1, 15-2...15-n corresponding to plural access detecting means. Then access to plural addresses (AD1, AD2...ADn) which is repeated at a specific period is detected by an address decoder unit circuit 15 and the clear signal generating circuit 11 detects abnormality according to the time-up time of the abnormality monitor timer circuit and plural access detection signals A1, A2...An outputted by the address decoder unit circuit 15 and outputs alarm signal.
申请公布号 JPH05210539(A) 申请公布日期 1993.08.20
申请号 JP19920038452 申请日期 1992.01.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 HATANO MASAHIRO
分类号 G06F11/00;G06F11/30;G06F11/32 主分类号 G06F11/00
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