| 摘要 |
<p>PURPOSE:To reduce an erasing time during the test operation of a flush memory. CONSTITUTION:The flush memory is provided with a verify voltage generating circuit 11 which generates a test erase verify voltage in accordance with the test erase verify command outputted from a command decoder 13 in response to an external signal during a test operation. The test erase verify voltage is higher than the erase verify voltage generated during a normal operation and an erase verify is executed by applying a test erase verify voltage to an X decoder 4 and a Y decoder 5. Since the test erase verify voltage is higher than the erase verify voltage which is used in a normal operation, it is judged that an erase is performed with a smaller number of erase pulses than a normal operation and thus, an erase time is reduced in a test operation.</p> |
