发明名称 SYNCHRONOUS DETECTOR
摘要 PURPOSE:To decide the establishment of a carrier phase locked loop in a short time. CONSTITUTION:A PLL consisting of an oscillator 1, a demodulator 2, a detector 3, and a filter 4 establishes the carrier phase locked loop when a two-phase phase modulation signal is inputted to a demodulator 2. A square circuit 5 squares an in-phase side demodulation signal outputted from the demodulator 2, and a square circuit 6 squares an orthogonal phase side demodulation signal outputted from the demodulator 2. A subtraction circuit 7 subtracts the output signal of the square circuit from the output signal of the square circuit 5, and an averaging circuit 8 averages the output signal of the subtraction circuit 7. As a result, all the noise components can be eliminated from the output of the averaging circuit 8 even when the noise component is included in the two-phase phase modulation signal inputted to the demodulator 2, and signal in accordance with the square of modulation data can be obtained. Therefore, adversely, when the averaging circuit 8 outputs a signal of constant level, the carrier phase locked loop has been established, and a phase locked loop detection decision circuit 9 outputs a detection decision signal at that time.
申请公布号 JPH05207083(A) 申请公布日期 1993.08.13
申请号 JP19920013492 申请日期 1992.01.29
申请人 NEC CORP 发明人 TSUDA HIROKI
分类号 H04L27/22 主分类号 H04L27/22
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