| 摘要 |
PURPOSE: To monitor an input clock signal through a phase locked loop(PLL) circuit and to continue the operation to switch the main input clock signal to a redundant clock signal when the main input clock signal gets invalid. CONSTITUTION: The PLL monitors the frequency of redundant and input clock signals and when one or the other gets invalid these signals are switched. Therefore, even when one input clock signal becomes faulty, a PLL 10 continues the normal operation. When two input clock signals 1 and 2 are turned faulty, until any one input clock signal is recovered, an internal reference signal maintains the PLL 10 in a nomical operating frequency and the loop quickly re-establishes the phase lock. In order to discriminate validity, the input clock signal is sampled and stored by a reference signal through a prescribed method. When the sample values of respective input clock signals after a sample period have the same logic state, these input clock signals are valid but when any one of samples of input clock signals after the sample period has a different logic state, the input clock signal is invalid. |
