Reducing clock skew in large-scale integrated circuits

摘要

In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.