| 摘要 |
<p>PURPOSE:To perform a high speed reading operation by providing two charging NMOS transistors connected in series and speedily charging them to near inversion voltage of a sense-amplifier. CONSTITUTION:When the potentials of a column select wire 9 and a word line 10 become a VDD level, a selection of a memory cell 6 is performed. If the potential VDATA of a data line 7 is an L level, an inverter circuit 4 of a bit line 8 detects the potential of the data line, the data become an H level and a charging is performed by load transistors 1 and 2 through an NMOS transistor 3. Then, charging NMOS transistors 11 and 12, which have a larger charging capability, are turned on and a charging is performed. Thus, the transition time of the data line 7 from an L level to an H level is reduced. Moreover, when the potential of the data line 7 reaches near a sense-amplifier inversion voltage VC, the transistors 11 and 12 are turned off and a charging is completed. Therefore, a high speed charging of the sense-amplifier and a high speed reading are possible.</p> |
