| 摘要 |
PURPOSE:To adjust data transmission delay time by increasing/decreasing buffer capacity by limiting write and read address counters by a buffer capacity control part, address load signal generation part and address comparison part. CONSTITUTION:After an input data signal 1 is converted to be parallel by a serial/parallel conversion part 2, the signal is inputted through a data bus D10 to a memory 3. At such a time, a write address to the memory 3 is inputted through a bus AD10 to an address selection part 4 and further, the address is applied to the memory 3 while being switched with a read address, which is inputted from a counter 14 through a bus AD11, by the selection part 4. A read timing signal generation part 9 generates a timing signal S10 for S/P conversion at the conversion part 2 and a timing signal S11 to the selection part 4 based on a write clock 8. Next, in the case of reading, the read address generated by the counter 14 is inputted to the memory 3 while being switched with the write address by the selection part 4, read data are outputted to a parallel/serial conversion part 5, and an output data signal 6 is outputted synchronously to a timing signal S12 from a read timing signal generation part 17. |
