| 摘要 |
This circuit comprises an operational amplifier A1 to the inputs of which are connected capacitors C1A, C1B, switches S4A, S4B, S5A, S5B, these capacitors being moreover connected between voltage sources VR+, VR and earth by switches S1A, S1B, S2A, S2B, the inverting and non-inverting inputs of the amplifier being connected respectively to its non-inverting and inverting outputs by integration capacitors C2A, C2B. There is moreover provision for a switch S6 for linking between the terminals of the capacitors C1A, C1B opposite the inputs of the operational amplifier, switches S3A, S3B, S6 for discharging the capacitors C1A, C1B and means L for generating, from clock signals and from the digital signal to be converted, signals 1, 2, 2+, 2- and 2c for control of the switches S4A, S4B, S5A, S5B, S6; S1A, S1B, S2A, S2B; S3A, S3B, S6 in order sequentially to cause charging of the capacitors C1A, C1B and either the transfer of their charges into the integration capacitors C2A, C2B, or their discharge depending on the differential voltage increments to be obtained between the outputs of the operational amplifier A1. <IMAGE>
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