| 摘要 |
<p>PURPOSE: To attain delay control in a desired degree by delay setting from outside by controlling the read/write address of a RAM, to effectively realize the delay of a digital signal. CONSTITUTION: A synchronizing counter 1 counts inputted data, and low-order 8-bits are inputted to a first tri-state buffer 3 as a row address to be controlled by a RAM signal. High-order 8-bits are inputted to an adder 2 as a column address, added with data D1 to D8 built in ROM inputted to terminal parts B0 to B7, and inputted to a second tri-state buffer 4 to be controlled by a CAS signal. Consequently, a read address with the time difference of about D7 to D0 from a write time is generated and outputted from final addresses A1 to A8 at the time of reading. A delay time is adjusted by varying these D0 to D7.</p> |
