发明名称 |
DYNAMIC MEMORY BIT LINE PRECHARGE SCHEME |
摘要 |
A method and apparatus for precharging DRAM bit lines and data buses from the same voltage source, eliminating a separate bit line precharge source and the bit line precharge conduction paths. The precharge source for the data buses is coupled to the data buses and at the same time access transistors normally used to couple the bit line logic voltage to the data buses are enabled, in order to cause coupling of the precharge voltage source through the data buses and the access transistors to the bit lines during a precharge interval. This both precharges and equalizes the voltage on both complementary data buses and both complementary bit lines.
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申请公布号 |
US5233560(A) |
申请公布日期 |
1993.08.03 |
申请号 |
US19910680834 |
申请日期 |
1991.04.05 |
申请人 |
FOSS, RICHARD C.;YONEYAMA, AKIRA |
发明人 |
FOSS, RICHARD C.;YONEYAMA, AKIRA |
分类号 |
G11C11/4094 |
主分类号 |
G11C11/4094 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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