| 摘要 |
PURPOSE:To provide an asynchronous pulse retiming circuit using only a given clock so as to convert the asynchronous pulse into a synchronizing pulse with one clock width. CONSTITUTION:An asynchronous pulse S1 is latched by a leading and a trailing of a clock CK given by two pre-stage flip-flop circuits 2, 3, output pulses S2, S3 of the pre-stage flip-flop circuits 2, 3 are given to an AND gate 4 and the clock CK is latched by a middle-stage flip-flop 5. An output pulse S5 of the middle stage flip-flop 5 is latched again by a clock of a post-stage flip-flop 6 to make retiming and an output pulse S6 of the post-stage flip-flop 6 and an inverse of pulse S7 of the output pulse S5 of the middle stage flip-flop 5 are given to an AND gate 8, in which a pulse, S8 synchronously with the clock CK with the asynchronous pulse S1 given thereto with one clock width is converted. |
