发明名称 Delay unit implemented by inverting circuits associated with capacitive load for increasing delay
摘要 A delay unit incorporated in a standard cell type semicustom-made integrated circuit comprises a plurality of complementary inverting circuits coupled in cascade for introducing a time delay into propagation of a signal, and a lead circuit coupled to one of the complementary inverting circuits for increasing the time delay, and the plurality of complementary inverting circuits and the load circuit are formed in and one a plurality of rectangular active areas defined by a thick field oxide film grown on a major surface of a semiconductor substrate, wherein the thick field oxide film penetrates into two of the rectangular active areas so as to form respective bifurcated portions, one of the complementary inverting circuits and the load circuit being formed in the bifurcated portions so that large channel resistance of the complementary inverting circuit and large capacitance of the load circuit are easily produced without changing the arrangement of the rectangular active areas.
申请公布号 US5229667(A) 申请公布日期 1993.07.20
申请号 US19910743636 申请日期 1991.08.12
申请人 NEC CORPORATION 发明人 SHIMIZU, NORIE
分类号 H01L27/092;H01L21/82;H01L21/8238;H01L27/02;H03K5/00;H03K5/13 主分类号 H01L27/092
代理机构 代理人
主权项
地址