Read circuit for large-scale dynamic random access memory

摘要

A circuit for reading and writing data to/from memory cells of a DRAM, based upon sense amplifiers formed of N-type and P-type FETs for each pair of bit lines of the DRAM and column switches formed of FETs for transferring data potentials to/from the bit line pairs, in which the current drive capability of the column switches is increased relative to the sense amplifiers during each write cycle and the current drive capability of the sense amplifiers is increased relative to that of the column switches during each read cycle, thereby ensuring satisfactory read and write operation even for a very large-scale DRAM operating with a low value of supply voltage.