发明名称 Timing clock signal reproducer with error signal generator - includes switch=off unit preventing integration of temporal error signal on basis of detected input abnormality
摘要 Incoming signals are digitised (100) to a fixed level (101) and mixed (102) with demodulation carrier signals (104) in quadrature to obtain a complex baseband signal (CRS), which is low-pass filtered (105), equalised (106) to compensate for transmission distortion, and compared (107) with a reference signal for decoding (CO). A timing error detector (200) is used with an integrator (201), frequency divider (202), oscillator (203), multiplier (211), another integrator (212), an adder (210), switch-off unit (300), control unit (301) and input abnormality detector (302). USE/ADVANTAGE - In facsimile or data transmission systems, rapid synchronisation between transmitter and receiver is reproducible even when the rhythm of timing varies markedly.
申请公布号 DE4300126(A1) 申请公布日期 1993.07.08
申请号 DE19934300126 申请日期 1993.01.05
申请人 RICOH CO., LTD., TOKIO/TOKYO, JP 发明人 MIYACHI, TATSUO, TOKIO/TOKYO, JP;UCHIYAMA, HIROKI, YOKOHAMA, KANAGAWA, JP
分类号 H04L27/00;H03L7/00;H04L7/00;H04L7/033;H04L27/22 主分类号 H04L27/00
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