| 摘要 |
<p>Virtual addressing is available to a co-processor (20) to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store (23, MS) and expanded store (24, ES), or both may be in ES (24), or both may be in MS (23). The co-processor (20) controls the asynchronous page movement in parallel with continuing execution of other instructions by the central processor (CP) which requested the page movement. Each page to be moved is specified by an MSB (Move Specification Block). A set of MSBs are addressed by a special type of channel control word (CCW) in a channel program containing one or more CCWs, some of which may address one or more sets of MSBs (one MSB set per CCW) to control the movement of any number of pages. The CPU executes a special ADM SSCH (start subchannel) instruction that passes the page move work to the co-processor (20) to perform the requested page transfer involving one or more sets of MSBs. Flag fields in source and sink specifications in each MSB contains a plurality of flag bits that define: the associated source or sink media, whether the specified address is to be translated as a virtual address or to be handled as an absolute address, whether replication of the source page(s) is to be done at the sink location, and whether the page(s) are to be erased by only accessing the sink pages to control the writing of a predetermined padding character, such as zero, through-out the content of the sink page(s). <IMAGE></p> |
