| 摘要 |
PURPOSE: To form a small memory cell region by employing a vertical magnetic film load transistor and mounting the interconnection of each layer and the electrode of a transistor with high density. CONSTITUTION: Six transistors memory cells have two nodes each having five interconnections. Four interconnections associated with each node 1, 2 are provided at the lower part of a trench. One of first interconnections is the current electrode of a transfer transistor 10. Second interconnection is the gate of a latch transistor 16, third interconnection is the drain electrode of a vertical TFT load transistor 18, fourth interconnection is the drain of a latch transistor 14, and fifth interconnection is connected with the gate of the vertical load transistor. Ten interconnections in a memory cell are entirely included in a region where both trenches are surrounded in combination. Fifth interconnection of the node 1 is included in the trench of the node 2 and fifth interconnection of the node 2 is included in the trench of the node 1. |
