Back bias voltage generating circuit for CMOS semiconductor device - has oscillator circuit delivering control signals for pair of pumping stages in parallel

摘要

The back bias voltage generating circuit has two pumping stages, each having NMOS stages (M1,M2,M5 and M6,M7,M10) coupled to a supply voltage (Vss). A control signal generator consisting of cross coupled NOR gates provides an oscillator mode supplying inputs via a gate (X4) to both pumping stages. The signals are fed via inverter chains (X1-X3,X6-X8) to the gating NMOS devices via capacitors (M4,M9). ADVANTAGE - Stable operation with steady level.