| 摘要 |
PURPOSE:To improve a check function of the counter and to reduce the circuit scale. CONSTITUTION:Plural counters 111, 112, 113 are operated in parallel by receiving a test mode signal of a test mode signal generating circuit 61. Thus, the normal operation counting a counter clock is switched to the test mode checking whether or not the normal operation is normally implemented. Furthermore, a counter clock generating circuit 63 generates a counter clock at a period sufficiently longer than the generating period of a synchronization clock of the integrated circuit in response to the number of flip-flops 31, 32, 33 being components of a synchronizing circuit 62. Then the edge of the counter clock generated by the counter clock generating circuit 63 is detected and data generated from the counters 111, 112, 113 when the edge is detected are set to the flip-flops 21, 22, 23, 28. |
