| 摘要 |
<p>PURPOSE:To generate no unevenness even when a heat process is performed by forming a 1st gate wiring layer of a low-resistance layer containing alumi num and covering the 1st gate wiring layer with a 2nd gate wiring layer. CONSTITUTION:The 1st gate wiring layer 21 containing aluminum and the 2nd gate wiring layer 22 which covers the 1st gate wiring layer 21 are provided as a gate electrode bus 3. Namely, the gate electrode bus 3 are wired in two layers and the 1st gate wiring layer 21 contains aluminum, so the gate electrode bus 3 has low resistance. Further, the 1st gate wiring layer 21 is covered with the 2nd gate wiring layer 22 made of chromium, etc., no unevenness (hillock) is formed even after the subsequent heat process and a plasma process, and a gate electrode 9 can be made flat.</p> |
