Converting rectangular data signals to transmission signals - indexing counter upon successive differences between data signal and delayed data signal and converting count into analogue output

摘要

A circuit receives a rectangular data signal (DS) and converts it into a transmission signal (S) of limited bandwidth using a time delay stage (25) and a counter stage (25). The latter counts forwards or backwards in response to clock pulses (C), provided by successive difference values between the data signal (DS) and the delayed data signal (DV) and is followed by a D/A converter providing analogue values representing the count values, used as the transmission signal (S). Pref. the data signal (DS) is delayed via a shift register indexed by the clock pulses (C). ADVANTAGE - Relatively simple circuit suitable for integration.