| 摘要 |
PURPOSE:To apply bit phase synchronization to an input data signal surely with respect to a system clock without being affected by a detection period of a state change point of the input data signal. CONSTITUTION:A selection section 10 delays sequentially external data and obtains n-kinds of data and its state change is detected from selection output data from the selection section 10 by a detection section 11, and a detection section 12 detects a phase difference with a system clock. A protection section 13 counting a phase difference detection signal updates the selection output from the selection section 10 via a control section 14 every time the count reaches a prescribed value into other signal thereby allowing the external data to be in phase synchronization with the system clock. |
