发明名称 RESETTING CIRCUIT
摘要 <p>PURPOSE:To form a power ON reset signal having a long continuing time while suppressing the increment of a loading area or cost and to accurately set up the continuing time. CONSTITUTION:When a power supply is turned on, a power ON reset circuit 1 outputs a low level reset signal 11 for a fixed period. Thereby a reset signal outputted from a reset signal forming circuit 3 is turned to the low level. Since the low level reset signal 11 is not inputted to a counter 2, the counter 2 enters a load value. When the reset signal is turned to the high level, the counter 2 starts to count up a clock signal 12, and when the count value reaches a prescribed value, outputs a low level counter output 14. The circuit 3 receives the signal 14 and turns the reset signal 15 to the high level.</p>
申请公布号 JPH05143199(A) 申请公布日期 1993.06.11
申请号 JP19910305953 申请日期 1991.11.21
申请人 NEC CORP 发明人 KOYAMA YUICHI
分类号 G06F1/24 主分类号 G06F1/24
代理机构 代理人
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