发明名称 STRUCTURE OF CHIP CARRIER
摘要 PURPOSE:To reduce a voltage drop in a circuit board to be used for a chip carrier and to decrease a signal propagation delay and noise by employing a straight line wiring from a chip terminal to external connection terminal thereby minimizing the length of inner wiring of a chip carrier board. CONSTITUTION:A chip carrier connects a chip 1 to a board 2 via a solder bump 10 and a land 9, and further airtightly seal the chip 1 via the board 2, a first metal frame 5, a second metal frame 6 and a heat sink 4. The board 2 has a straight through hole 11, which connects the land 9 to an external connection terminal 3 for connecting the chip 1 to the outside of chip carrier 2 via a straight conductor wiring, thereby mostly shortening the wiring length. Thus, a signal wiring length in the board 2 becomes short to reduce a signal delay and noise. The wiring length of a power source is also shortened, and a voltage drop is reduced.
申请公布号 JPH05144971(A) 申请公布日期 1993.06.11
申请号 JP19910329586 申请日期 1991.11.18
申请人 NEC CORP 发明人 MIYAZAKI YUICHI
分类号 H01L23/12;H01L23/40 主分类号 H01L23/12
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