MEMORY CONTROL UNIT OF COMPUTER SYSTEM BY USING DYNAMIC RAM

摘要

The system for using a page mode DRAM controller to reduce an access time comprises a processor (10) having signals for dividing the memory area into program, data and stack areas, an area decoding unit (21) for decoding the memory area dividing signal from the processor, an address decoding unit (22) for applying an enable signal (50) to the unit (21), a first page mode DRAM controller (31) for controlling a first DRAM (41) for program area, a second page mode DRAM controller (32) for controlling a second DRAM (42) for data area, and a third page mode DRAM controller (33) for controlling a third DRAM (43) for stack area.