发明名称 Imaging device with drive voltage dependent on external light intensity
摘要 A solid-state imaging device increases the SN ratio of a signal even when external light intensity is low. The solid-state imaging device includes a sensor circuit that includes a light-receiving element, a first transistor that controls connection between a first wiring and a node in which the amount of accumulated charge is determined by the amount of exposure to the light-receiving element, a second transistor whose on or off state is selected in accordance with the potential of the node, and a third transistor that controls connection between a second wiring and a third wiring together with the second transistor; a central processing unit that selects a first driving method or a second driving method in accordance with external light intensity; and a controller that controls a potential supplied to the gate of the first transistor in accordance with the first driving method or the second driving method.
申请公布号 US9379138(B2) 申请公布日期 2016.06.28
申请号 US201414332905 申请日期 2014.07.16
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Ikeda Takayuki;Kurokawa Yoshiyuki
分类号 H01L27/146;H01L27/12;H01L29/786 主分类号 H01L27/146
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a light-receiving element; a first transistor; a second transistor; a third transistor; a CPU; and a controller, wherein one of electrodes of the light-receiving element is electrically connected to a node, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the node, wherein a gate of the second transistor is electrically connected to the node, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected to a wiring, wherein the wiring is electrically connected to the CPU, wherein the CPU is electrically connected to the controller, wherein the controller is electrically connected to a gate of the first transistor, wherein the first transistor comprises an oxide semiconductor layer in a channel formation region, wherein an oxide layer containing oxygen at a proportion higher than a stoichiometric composition is located over the source electrode, the drain electrode and the oxide semiconductor layer, wherein the CPU is configured to select a first driving method in which a third potential which is higher than a first potential and lower than a second potential is supplied to the gate of the first transistor in accordance with an external light intensity, wherein the controller is configured to supply the third potential to the gate of the first transistor in accordance with a result of a selection of the CPU, wherein the first potential makes the first transistor be in an off state, and wherein the second potential makes the first transistor be in an on state.
地址 Atsugi-shi, Kanagawa-ken JP