发明名称 Method for depositing a diffusion barrier layer and a metal conductive layer
摘要 We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
申请公布号 US9390970(B2) 申请公布日期 2016.07.12
申请号 US200711733671 申请日期 2007.04.10
申请人 APPLIED MATERIALS, INC. 发明人 Chiang Tony;Yao Gongda;Ding Peijun;Chen Fusen E.;Chin Barry L.;Kohara Gene Y.;Xu Zheng;Zhang Hong
分类号 H01L21/768;C23C14/04;C23C14/16;H01L21/285 主分类号 H01L21/768
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising: (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate; (b) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate; (c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts the barrier material remaining at the bottom of the plurality of vias; and (d) precleaning the wafer substrate prior to (a), wherein at least part of (a) and all of (b) are performed in the same processing chamber.
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