发明名称 Partitioned data compression using accelerator
摘要 In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive input data to be compressed; select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores; perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; and provide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output. Other embodiments are described and claimed.
申请公布号 US9419647(B2) 申请公布日期 2016.08.16
申请号 US201414571658 申请日期 2014.12.16
申请人 Intel Corporation 发明人 Gopal Vinodh;Guilford James D.;Wolrich Gilbert M.;Cutter Daniel F.
分类号 H03M7/40;H03M7/30 主分类号 H03M7/40
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. A processor comprising: a plurality of hardware processing cores; and a compression accelerator coupled to the plurality of hardware processing cores, the compression accelerator to: receive input data to be compressed;select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores;perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; andprovide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output.
地址 Santa Clara CA US