| 摘要 |
<p>PURPOSE:To reduce the memory capacity by performing a decoding process with a clock of a picture element rate according to code length data outputted from a storage part at a specific speed. CONSTITUTION:An image signal is converted into a small-correlation coefficient such as a DCT coefficient and the variable length code data obtained by variable length encoding are stored in a temporary storage part 210. This device has a storage part 210 which can output the data in M-bit units at a speed faster than the picture element rate and a code length detection and decoded value conversion part 220. Here, M is the maximum number of bits among the variable length code data for respective coefficients. Further, the conversion part 220 detects the code lengths of the variable length code data for information on the respective coefficients and outputs M-bit variable length code data from a bit position following the encoded data which is decoded. Consequently, the decoding is performed with the clock and the memory capacity for conversion to the picture element rate is reducible without increasing the operation speed.</p> |
