| 摘要 |
PURPOSE:To provide a two-phase clock generation circuit capable of obtaining output which the pulse widths of a two-phase pulse from a low frequency to a high frequency are almost same. CONSTITUTION:When a clock signal to be a reference is inputted, a first ring oscillator generates an oscillation signal by receiving a signal synchronizing with the clock signal and a second ring oscillator generates an oscillation signal by receiving a signal which is different from the clock signal in phase. D type flip-flop(DFF) 3a, 3b are reset by the oscillation signals from the first and second ring oscillators, respectively, immediately after the clock signal is inputted and generates clocks, respectively. The flip-flop 3a, 3b generates a two-phase pulse wherein the high level period and the low level period of these two clocks do not overlap each other. |
