| 摘要 |
The input circuit for resetting latch and register according to user-designating logic data comprises first to fourth transmission lines (CS1,CS2,CS3,CS4), an input line, latch (30) and D flip-flop (31) connected to the input line, a transmission gate circuit (32) for transmitting the outputs of the input line, latch (30) and D flip-flop (31) under the control of the transmission lines, an OR gate (33) for receiving a power-on reset signal and an async. product term signal to transmit a logic sum to the reset terminals of the latch and D flip-flop (30,31), and a multiplexer (34) for multiplexing the product term signal and ILE/ICLK signal under the control of the fourth transmission line (CS4).
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