发明名称 |
MOS device having a well layer for controlling threshold voltage |
摘要 |
The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.
|
申请公布号 |
US5210437(A) |
申请公布日期 |
1993.05.11 |
申请号 |
US19920925411 |
申请日期 |
1992.08.10 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SAWADA, SHIZUO;IWASAKI, SEIKO |
分类号 |
H01L21/266;H01L21/336;H01L21/8234;H01L29/10 |
主分类号 |
H01L21/266 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|