| 摘要 |
A processor chip for adding a first integer having a plurality of groups of bits to a second integer having a plurality of groups of bits modulo a fourth integer having n-bits. The first integer plus the second integer equals a third integer. The processor chip includes a first register for storing the first integer, a second register for storing the second integer, and feedback register for storing a feedback number. The feedback number is the two's complement of the fourth integer. A plurality of full adders is coupled to the first register and the second register, and adds each group of bits of the first integer to the corresponding group of bits of the second integer, to generate the third integer. The bits of each group are added asynchronously during a time period. Sequentially, a second group of bits of the first integer are added to the corresponding second group of bits of the second integer. The processor chip also multiplies the first integer by the second integer wherein the full adders sequentially add each group of bits of the second integer to each corresponding group of bits of the third integer, in response to the least significant bit position of the first integer shifted right from the first register. The processor chip can exponentiate a first integer having n-bits by a second integer having m-bits, wherein the first integer raised to the power of the second integer equals a third integer. The exponentiation is preformed with successive applications of the multiplication operation.
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