发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To prevent the delay of synchronous hunting by providing a retiming circuit for outputting a holding mask signal, and a logic circuit for inhibiting the output of a hunting holding signal. CONSTITUTION:This circuit is provided with a synchronizing pattern detecting circuit 11, a timing pulse generating circuit 12, a frame pulse generating circuit 13, a synchronization counting circuit 14, and a synchronization protecting circuit 15. Also, the circuit is provided with a retiming circuit 16 for outputting a holding mask signal 1i when a synchronization counting signal 1h outputted from the synchronization counting circuit 14 is counted and reaches a counting value N-1, and a logic circuit for inhibiting an output of a hunting holding signal 1j by the holding mask signal 1i outputted from the retiming circuit 16. In such a way, since the hunting holding signal 1j is temporarily inhibited, a hunting delay time is not added to a synchronization reset time. Accordingly, the delay of synchronous hunting is prevented and the synchronization reset time can be shortened.</p>
申请公布号 JPH05110557(A) 申请公布日期 1993.04.30
申请号 JP19910266546 申请日期 1991.10.15
申请人 NEC CORP;NEC MIYAGI LTD 发明人 MATSUOKA ISAO;SATO NOBUYUKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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