发明名称 SIGNAL DELAY CIRCUIT
摘要 <p>PURPOSE:To provide the signal delay circuit delaying only a trailing or a leading of an input signal in which the input signal repetitively inputted at a high speed and a current consumption is not increased. CONSTITUTION:Gates of P and N-channel MOS transistors(TRs) 1,2 are connected together to form an input terminal 6 and sources of both MOS TRs 1, 2 are connected respectively to a power supply VDD and GND, and a resistor 3 is connected between drains of both MOS TRs 1, 2. Then a capacitor 4 whose one terminal connects to GND and a waveform shaping circuit 5 are connected to the drain of the N-channel MOS TR 2 and an output of the waveform shaping circuit 5 is used for an output terminal 7.</p>
申请公布号 JPH05110396(A) 申请公布日期 1993.04.30
申请号 JP19910294765 申请日期 1991.10.16
申请人 OLYMPUS OPTICAL CO LTD 发明人 KUSAZAKI YUKIO
分类号 H03K5/13 主分类号 H03K5/13
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