发明名称 SYSTEM FOR DIVIDING PROCESSING TASKS INTO SIGNAL PROCESSOR AND DECISION-MAKING MICROPROCESSOR INTERFACING
摘要 Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) (10) and tasks for a decision-making microprocessor (2120). The SPROC is provided with a non-inter- rupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the use r's design. In automatically implementing the block diagram into silicon, the SPROC programming/developing environment accounts for and provides software connection and in- terfaces with a host microprocessor (2120). The programming environment pref erably includes: a high-level computer screen en- try system which permits choosing entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library (2015) which provides source code representing the functional b locks; and a signal processor scheduler/compiler (2040) which uses the functional block cell library (2015) and the informati on entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the SPROC. as well as a symbol table which provides a memory map which maps SPROC addre sses to variable names which the microproces- sor (2120) will refer to in separately compiling its program.
申请公布号 CA2120232(A1) 申请公布日期 1993.04.29
申请号 CA19922120232 申请日期 1992.10.14
申请人 发明人
分类号 G06F15/16;F02B75/02;G06F;G06F9/06;G06F9/30;G06F9/32;G06F9/355;G06F9/38;G06F9/44;G06F9/45;G06F11/36;G06F13/28;G06F15/173;G06F15/177;G06F15/78;G06F15/80;G06F17/50;(IPC1-7):G06F9/40;G06F9/00 主分类号 G06F15/16
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