发明名称 |
PARALLEL DATA OUT-PUT CIRCUIT |
摘要 |
The parallel data output circuit can output the bits of data in a greater number than the number of predetermined bits of data. The circuit comprises first output port (10) having data output unit (11-14) for 4 bits of parallel data (DA10-DA13), a data selection unit (20) having multiplexers (21-24) for selectively outputting 4 bits of parallel data (DA14-DA17) and (DB10-DB13) according to a 8 bit output control signal (IUM), a second output port (30) having data output unit (31-34) for outputting the output data of unit (20), a first enable control unit (40) for receiving address signals (A0-A7) to transmit an enable signal (ENA10) to the port (10), and a second enable control unit (50) for receiving the address signals (A0-A7) and output control signal (IUM) to transmit an enable signal (ENB10) to the port (30).
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申请公布号 |
KR930003415(B1) |
申请公布日期 |
1993.04.29 |
申请号 |
KR19910000633 |
申请日期 |
1991.01.16 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JO, SONG - IL;YANG, HYONG - SOK;SHIN, KI - HO;SHIN, MYONG - CHOL |
分类号 |
G06F13/38;(IPC1-7):G06F13/38 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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